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V ITEC ? 1 . 25 V
I TEC =
ADN8831
R A
Data Sheet
TEMPERATURE LOCK INDICATOR
The TMPGD (Pin 11) outputs a logic high when the OUT1 (Pin 4)
voltage reaches the IN2P (Pin 5) temperature setpoint (TEMPSET)
voltage. The TMPGD has a detection range of ±25 mV and a
10 mV typical hysteresis. This allows direct interfacing either to
the microcontrollers or to the supervisory circuitry.
SOFT START ON POWER-UP
The ADN8831 can be programmed to ramp up for a specified
time after the power supply is turned on or after the SD pin is
deasserted. This feature, called soft start, is useful for gradually
increasing the duty cycle of the PWM amplifier. The soft start
time is set with a single capacitor connected from SS (Pin 14) to
ground. The capacitor value is calculated by the following
equation:
τ SS = 150 × C SS
w here:
C SS is the value of the capacitor in microfarads.
τ SS is the soft start time in milliseconds.
To set a soft start time of 15 ms, C SS is to equal 0.1 μF.
SHUTDOWN MODE
The shutdown mode sets the ADN8831 into an ultralow current
state. The current draw in shutdown mode is typically 8 μA.
The shutdown input, SD (Pin 16), is active low. To shut down
the device, drive SD to logic low. Once a logic high is applied,
the ADN8331 is reactivated after the time delay set by the soft
start circuitry. Refer to the Soft Start on Power-Up section for
more details.
STANDBY MODE
The ADN8831 has a standby mode that deactivates a MOSFET
driver stage. The current draw for the ADN8831 in standby
mode is less than 2 mA. The standby input SS/SB (Pin 14) is
active low. After applying a logic high, the ADN8331 reactivates
following the delay. In standby mode, only SYNCO (Pin 15) has
a clock output. All the other function blocks are powered off.
TEC VOLTAGE/CURRENT MONITOR
The TEC real time voltage and current are detectable at VTEC
ADN8831
Current Monitor
ITEC (Pin 29) is an analog voltage output pin with a voltage
proportional to the actual current through the TEC. A center
ITEC voltage of 1.25 V corresponds to 0 A through the TEC.
The output voltage is calculated using the following equation:
V ITEC = 1 . 25 V + 25 × ( V LFB ? V CS )
The equivalent TEC current is calculated using the following
equation:
25 × R SENSE
MAXIMUM TEC VOLTAGE LIMIT
The maximum TEC voltage is set by applying a voltage at
VLIM (Pin 31) to protect the TEC. This voltage can be set with
a resistor divider or a DAC. The voltage limiter operates in
bidirectional TEC voltage, and cooling and heating voltage.
Using a DAC
Both the cooling and heating voltage limits are set at the same
levels when a voltage source directly drives VLIM (Pin 31).
The maximum TEC voltage is calculated using the following
equation:
V TEC ( MAX ) = 5 × V VLIM
where:
V TEC (MAX) is the maximum TEC voltage.
V VLIM is the voltage applied at VLIM (Pin 31).
Using a Resistor Divider
Separate voltage limits are set using a resistor divider. The
internal current sink circuitry connected to VLIM (Pin 31) draws
a current when the ADN8831 drives the TEC in a heating
direction, which lowers the voltage at VLIM (Pin 31). The
current sink is not active when the TEC is driven in a cooling
direction; therefore, the TEC heating voltage limit is always
lower than the cooling voltage limit.
V REF
VLIM
VLIM
R B
(Pin 30) and ITEC (Pin 29), respectively.
Voltage Monitor
I SINK
FREQ
VTEC (Pin 30) is an analog voltage output pin with a voltage
proportional to the actual voltage across the TEC. A center
VTEC voltage of 1.25 V corresponds to 0 V across a TEC. The
output voltage is calculated using the following equation:
V VTEC = 1 . 25 V + 0 . 25 × ( V LFB ? V SFB )
Rev. A | Page 13 of 20
R FREQ
Figure 16. Using a Resistor Divider
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